1. Technical Field
This disclosure relates to a method of driving a program operation in a nonvolatile semiconductor memory device.
2. Description of the Related Art
A general data programming operation in a nonvolatile semiconductor memory device is carried out by controlling a threshold voltage of a memory cell selected for programming. The word-line of the selected memory cell is supplied with a predetermined program voltage and a corresponding bitline is controlled according to data to be programmed. During this condition, the control for the threshold voltage of the selected memory cell is dependent on a voltage level of the corresponding bitline.
FIG. 1 is a timing diagram illustrating a conventional method of driving a program operation in a nonvolatile semiconductor memory device. In the conventional method there is a memory cell programming period P10 and a verifying period P20. During the memory cell programming period P10 the threshold voltage of a selected memory cell is increased by means of the voltage of a bitline BL that is connected to the selected memory cell. During this period, the bitline BL is charged with a ground voltage VSS (i.e., a programmable condition), while another bitline disconnected from the selected memory cell is set to a power source voltage VDD (i.e., program-inhibit condition). In the verifying period P20, a confirmation is made to check whether the selected memory cell, which has been processed in the programming period P10, is conditioned correctly, or has failed to be properly programmed. During this period, a data bit of the selected memory cell is loaded on the corresponding bitline BL. If the selected memory cell is determined to be in a program fail state in the verifying period P20, then the memory cell programming period P10 is repeated to correctly program the selected memory cell.
As shown in FIG. 1, during the sequence of the conventional program driving operation, a bitline discharging period P31 follows the memory cell programming period P10. Additionally, another bitline discharging period P32 follows the verifying period P20 and precedes the memory cell programming period P10′. In the discharging periods P31 and P32, all the bitlines BL drop to the ground voltage VSS. Also, during the threshold-voltage control processes T12 and T12′, the word-line WL of the selected memory cell is supplied with a program voltage VPGM to control its threshold voltage. During a bitline reading process T22, the bitline BL voltage is determined by the data bit of the selected memory cell.
Due to the conventional method of driving a program operation in a nonvolatile semiconductor memory device, the discharging period P31 or P32 precedes a bitline precharging process T21 to re-precharge the bitline BL or a bitline setup process T11′ to reset the bitline BL.
Thus, in the conventional method of driving a program operation, increased program time and unnecessary current consumption are required to program data for the selected memory cell due to the presence of two bitline discharging periods P31 and P32.